1. Field of the Invention
The present invention relates to a static semiconductor memory device (SRAM), and more particularly to voltage boosting circuit used for the memory device for the purpose of lowering the power supply voltage.
2. Description of the Related Art
In recent years, with an increase in usage of portable equipment of semiconductor device, advancements have been made in compactness and power savings.
For this reason, a voltage boosting circuit has been used in semiconductor devices for the purpose of enabling battery-powered operation.
In the Japanese Unexamined Patent Publication (KOKAI)No. 3-273594, there is a disclosure of technology for a semiconductor device that has a voltage boosting circuit that enables low-voltage operation by raising the voltage within the semiconductor device to higher than the externally applied power supply voltage.
The technology that is disclosed in the Japanese Unexamined Patent Publication (KOKAI)No. 3-273594 is directed to a dynamic semiconductor memory device (DRAM), and in this technology, as shown in FIG. 7, to be described later, the semiconductor memory has a voltage boosting circuit that makes use of a charge pump, so as to improve low-voltage data amplification and memory cell writing, and the like.
In the Japanese Unexamined Patent Publication (KOKAI)No. 4-212788, there is a disclosure of technology for using the voltage boosting circuit that is shown in FIG. 7 in a four-transistor static semiconductor memory (SRAM) device, whereby an SRAM is implemented which, while maintaining a high level of integration, is capable of low-voltage reading and writing, in which the word line is stepwise increased in voltage only at the time of writing of data into the memory cell.
Additionally, in the Japanese Unexamined Patent Publication (KOKAI)No. 5-120882, there is a disclosure of a SRAM with TFT memory cells that is capable of raising the voltage during a wait time, using a small electrical power.
The reason why it is necessary to boost the word line voltage using a voltage boosting circuit in an SRAM that operates at low voltage is as follows.
FIG. 11 shows circuit that is a combination of a four-transistor memory cell 17, which uses the four transistors Qa, Qb, Qc, and Qd, and a pre-charge circuit 16, which uses the three transistors Qe, Qf, and Qg.
In FIG. 11, the reference numeral wL denotes a word line, the n-type transistors Qa and Qc functioning as memory cell transfer gates, and the n-type transistors Qb and Qd functioning as memory cell drivers. The resistive elements R1 and R2 are load resistances, D and DB are bit lines, and the two transistors Qe and Qf are pre-charge transistors.
FIG. 12 and FIG. 13 will be used to described the difference between having or not having a boosted potential when data writing is done in a memory cell such as shown in FIG. 11.
FIG. 12(a) shows the case in which a data write operation is performed without raising the voltage on the word line, and FIG. 13(a) shows the case in which a data write operation is performed with the voltage on the word line raised. FIG. 12(b) and FIG. 13(b) show the cases in which after the data write operation was performed under the conditions as shown in FIG. 12(a) and FIG. 13(a), the data reading operation was performed, respectively, without putting an intervening wait time, following the data write operation having been completed.
In the drawings, in the data before the write operation, the node V2 is at the power supply voltage VCC and the voltage at the node V1 is at ground, with the bit lines D and DB being supplied by voltage from the pre-charge transistors Qe and Qf, so that their voltages are at the VCC level.
First, the case in which data is to be written so as to cause a reversal of the potentials on the nodes V1 and V2 of the memory cell 17 will be described.
In this case, the level on the word line WL1, which is the selection line of the memory cell 17 is caused to change to the high level, and the level on the bit line DB is caused to be low, so that data is written into the memory cell 17.
When this is done, the node V2 is at the ground level, the same as the bit line DB, while the node V1, because of the threshold voltage of the cell transfer gate, cannot be boosted up to the power supply voltage VCC, and is brought to close to the power supply voltage VCC by just the current that is supplied through the load resistance R1.
Then, in the case in which data is read from the memory cell 17, the transistors Qe, Qf, and Qg of the pre-charge circuit 16 are switched on simultaneously in order to reset the data of another memory cell 17, so that the potential on the bit lines D and DB is pre-charged and rises to the power supply voltage VCC.
Next, in the case in which, after data writing, data which was written into a memory cell is to be read out immediately, as shown in FIG. 12(b), the level on the word line WL1, similar to the case of data writing, is changed to the high level, but because the reading of data is done without raising the node V1 to the power supply voltage VCC, the data that was written with the gate-source voltage of the transistor Qd as a memory cell driver being low is read out.
For this reason, there is a drop in the current capacity in comparison to the case in which the gate voltage of the transistor Qd is at the power supply voltage VCC, and the electrical charge that flows from the transfer gate Qc of the bit line DB causes the potential at the node V2 to rise.
In response to this rise in potential, the potential at the node V1 drops, so that there is only a very small difference in potential between the nodes V1 and V2. This impairs the holding of data in the memory cell at a low voltage.
To solve the above-noted problem, as shown in FIG. 13(a), the level on the word line is raised to the raised potential VBB, thereby raising it to above the threshold voltage of the transfer gate Qa, the result being that level on the node V1 at the time of writing is raised to the power supply voltage VCC.
By doing this, as shown in FIG. 13(b), even if data is read immediately after it is written, because of the large difference in potentials between the nodes V1 and V2, the cell data is not destroyed, even at a low voltage.
The configuration of the voltage boosting circuits all make use of the charge on a capacitor, a capacitor being charged up so as to produce a voltage that is greater than the externally applied power supply voltage, the raised potential Va being a function of the external power supply voltage VCC as shown below. EQU Va=(Ca/(Cx+Ca)).times.VCC+VCC (Equation 1)
In the above, Ca is the boot capacitance internal to the voltage boosting circuit, and Cx is the load capacitance that is to be raised to the raised potential.
As can be seen from Equation 1, in order to make the raised potential high, it is necessary to make the boot capacitance Ca higher than the load capacitance Cx. However, in order to make the chip size small and reduce the cost, it is difficult to make this boot capacitance Ca large.
For this reason, the three above-described prior art examples use a ring oscillator and a configuration in which the voltage is raised in steps.
The voltage boosting circuit that is shown in FIG. 7 is formed by the combination of a ring oscillator that is implemented by a NAND circuit B1 and the inverters B2 through B6, and a charge pump circuit 2, which is implemented by transistors QB1 and QB2 and a charge-amplifier capacitor CB1. The operation of the voltage boosting circuit shown in FIG. 7 will be described using FIG. 10.
In the voltage boosting circuit that is shown in FIG. 7, after the write start signal WCE changes to the high level, the ring oscillator 1 starts to operate, the output signal ROC from the ring oscillator 1 oscillating with an oscillation period that is established by the delays of the NAND circuit B1 and the inverters B2 through B5.
Before oscillation, the node Vb, which is one electrode side of the capacitor CB1 of the charge pump circuit 2 is stable at a potential that is established by the threshold voltage of the transistor QB1. When the oscillation signal ROC is input, the node Vb is raised to a potential difference that is the same as the supply voltage VCC.
By doing the above, the transistor QB2 goes into the on state, and the output voltage Va from the voltage boosting circuit also rises.
However, as indicated by Equation 1, if the output load on the output voltage Va from the voltage boosting circuit is large, it is not possible for the voltage to rise all at once to the raised potential VBB, the voltage Va rather being raised by a number of oscillation signal ROCs so that it reaches the boosted potential VBB.
The oscillation period that is required for the above operation can be determined by applying Equation 1. For example, for a boot capacitance Ca of 50 pF and a load capacitance Cx of 100 pF, if the power supply voltage VCC is 2 V and the transistor QB1 and QB2 threshold voltages are 0.5 V, the required raised voltage VBB would be 2.8 V.
First, the potential to which the voltage is raised at the first voltage boosting operation is as follows. EQU Va=(50/(100+50).times.2+(2-0.5)=2.17 V Equation (2)
Next, the potential to which the voltage is raised by the second voltage boosting is as follows. EQU Va=(50/(100+50).times.2+2.17=2.83 V Equation (3).
Thus, as shown in FIG. 10, the required raised voltage VBB is obtained by two voltage boosting operations.
In general, a ring oscillator is formed by an odd number of inverters, and the operating speed of the ring oscillator is lower the lower the voltage is made.
For this reason, the period of the ring oscillator becomes large, so that the time required for voltage to be boosted to the desired raised voltage is delayed as the voltage is reduced and this delay representing a slowing of the speed of writing data.
Because of the above-noted phenomenon, there was a disclosure in the Japanese Unexamined Patent Publication (KOKAI)No. 5-325578 of technology, as shown in FIG. 8, for increasing up the period of the ring oscillator as the voltage becomes lower, as a solution for the problem of slowed-down writing.
In the technology that is shown in FIG. 8, a fixed-voltage potential Vref, which is not dependent upon the power supply potential, is used, the gate potentials of depression-type n-channel transistors T1 through T5 being given a dependency that is the opposite to the external power supply potential VCC (that is, so that when the external power supply potential VCC becomes lower, the gate potentials of transistors T1 through T5 become higher), and the fact that the on-resistances of the transistors T1 through T5 drops with a drop in the power supply potential being used, so that period of the ring oscillator is shortened, the lower the voltage is.
The p-channel transistor QC2, which has the fixed-voltage potential Vref as its source input has a current capacity that is not dependent upon the power supply potential. H
However, the n-channel transistor QC1, which has the power supply voltage as an input to its gate exhibits a drop in current capacity accompanying a drop in power supply potential, the result being that the node C1 rises with a fall in the power supply potential.
Because of the above, the on resistances of the transistors T1 through T5 are made small, making it possible to speed up the period of the ring oscillator.
FIG. 9(a) and FIG. 9(b) show a voltage boosting circuit that is disclosed in the Japanese Unexamined Patent Publication (KOKAI)No. 5-325578, the method raising the voltage being therein basically the same as described above.
In FIG. 9, the capacitors CD1 and CD2, which are connected to the R1 and R2 inputs are voltage boosting capacitors, these corresponding to the capacitorCB1 shown in FIG. 7, the transistors QD3 and QD4 in FIG. 9 are for the purpose of holding the initial potential, these corresponding to the transistor QB1 shown in FIG. 7, and the transistors QD1 and QD2 of FIG. 9 are raised potential output gates, these corresponding to the transistor QB2 in FIG. 7.
A feature of the voltage boosting circuit that is shown in FIG. 9 is the use of separate capacitors CD3 and CD4 to raise the potentials of the boosted potential output gates by two voltage boosting operations over one period using the capacitors CD1 and CD2.
In the cases of FIG. 7 and FIG. 9, in an SRAM, in which it is not possible to make the capacitor size for the purpose of boosting the voltage large, it is necessary to use a plurality of voltage-boosting steps.
While the general purpose low-voltage operation is to enable battery-powered operation of SRAMs, limiting the AC current flowing in the ring oscillator is a condition for achieving a long battery-powered operating time.
In the above-described prior art, there is a means that operates faster the lower the voltage is, this being effective for high-speed, low-voltage operation of a SRAM.
In the case of repeated data writing operations under a lower voltage, however, the power consumption becomes large, leading to the problem that it is not possible to guarantee long periods of operation under battery power.
In the Japanese Unexamined Patent Publication (KOKAI)No. 8-287677, the technology disclosed is directed to a DRAM, and the technology disclosed in the Japanese Unexamined Patent Publication (KOKAI)No. 8-287677 is that of a configuration in which the voltage boosting circuit is caused to operate during the wait time of the DRAM.
However, with the technology that is disclosed in the Japanese Unexamined Patent Publication (KOKAI)No. 8-287677, the frequency is changed regardless of whether the DRAM is waiting or operating, and if this technology is applied to an SRAM, the current consumption will become large, leading to the problem of not being able to guarantee long periods of operation under battery power.
Additionally, in the case in which the voltage boosting circuit is to operate a large number of times before the raised potential is reached, because it is necessary to provide a plurality of voltage boosting circuit stages, there is the problem of not being able to achieve a circuit placement that fits in a compact surface area.
On the other hand, the Japanese Unexamined Patent Publication (KOKAI)No. 5-313795 discloses a semiconductor integrated circuit which can reduce an amount of consumption current during a standby period.
And in that, a charge pump can be selectively driven by a selection circuit which can selectively supply low frequency oscillating signal generated by an external oscillator or high frequency oscillating signal generated by an internal oscillator in response to a HALT signal.
Accordingly, it is an object of the present invention to provide a semiconductor memory device which can be driven under a low voltage and in which control is performed utilizing an internal command signal so that the period of a ring oscillator is shortened during the period required to reach the raised potential so as to speed up operation, and further so that after the completion of the raising of the voltage, the ring oscillator period is lengthened, thereby achieving a reduction in power consumption.